IMPLEMENTATION OF FUNCTIONAL BLOCK RADIO UNIT BASED ON SYSTEM-ON-CHIP
DOI:
https://doi.org/10.31489/2023No4/74-80Keywords:
Field-Programmable Gate Array, Zynq, Fifth Generation New Radio, Radio Unit, Orthogonal Frequency-Division Multiple AccessAbstract
This article discusses the implementation of the Radio Unit functional block based on the System-on-Chip. The primary focus was on integrating Radio Unit blocks such as modulation and Fast Fourier Transform on Field-Programmable Gate Array. Technical aspects of design, module testing, and Radio Unit block performance optimization are thoroughly examined. The results demonstrate that when separating the functionality of the 7.3 technology Fifth Generation (5G) radio block, the modulation module uses the minimum Field-Programmable Gate Array resources compared to other blocks. The Fast Fourier Transform block can meet delay requirements at the maximum Field-Programmable Gate Array size and clock frequency of 250 MHz. This article serves as a resource for engineers and researchers interested in optimizing the development and integration process of high-performance functional blocks in modern radio systems.
References
Bishop J., Chareau J. M., Bonavitacola F. Implementing 5G NR features in FPGA. IEEE, Proceeding of the European Conference on Networks and Communications (EuCNC), 2018, pp. 373 – 379. doi:10.1109/EuCNC.2018.8443214.
Ricart-Sanchez R., Malagon P., Salva-Garcia P., Chirivella-Perez T., Wang Q., Alcaraz-Calero J. M. Towards an FPGA-Accelerated programmable data path for edge-to-core communications in 5G networks. Journal of Network and Computer Applications, 2018, Vol. 124, pp. 80 – 93. doi:10.1016/j.jnca.2018.09.012.
Visconti P., Velazquez R., Del-Valle C.S., Fazio R. FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review. Telecommunication Computing Electronics and Control, 2021, Vol. 19, Part 4, pp. 1291 – 1306. doi:10.12928/telkomnika.v19i4.18400.
Kumar V., Mukherjee M., Lloret J. Reconfigurable architecture of UFMC transmitter for 5G and its FPGA prototype. IEEE, Systems Journal, 2019, Vol. 14, Part 1, pp. 28 – 38. doi:10.1109/JSYST.2019.2923549.
Ferreira M.L., Ferreira J.C. An FPGA-oriented baseband modulator architecture for 4G/5G communication scenarios. Electronics, 2018, Vol. 8, Part 1, pp. 2. doi:10.3390/electronics8010002.
Lin X. Li J., Baldemair R., Cheng JF. T., Parkvall S., Larsson D.C., Koorapaty H., Frenne M., Falahati S., Grovlen S., Werner K. 5G new radio: Unveiling the essentials of the next generation wireless access technology. IEEE, Communications Standards Magazine, 2019, Vol. 3, Part 3, pp. 30 – 37. doi:10.1109/MCOMSTD.001.1800036.
Larsen L.M.P., Checko A., Christiansen H.L. A survey of the functional splits proposed for 5G mobile crosshaul networks. IEEE, Communications Surveys & Tutorials, 2018, Vol. 21, Part 1, pp. 146 – 172. doi:10.1109/COMST.2018.2868805.
Borromeo J.C., Kondepu K., Andriolli N., Valcarenghi L. FPGA-accelerated SmartNIC for supporting 5G virtualized Radio Access Network. Computer Networks, 2022, Vol. 210, pp. 108931. doi:10.1016/j.comnet.2022.108931.
Coutinho F.D.L., Silva H.S., Oliveira A.S.R. FPGA-based Design and Optimization of a 5G-NR DU Receiver. IEEE, Telecoms Conference, 2021, pp. 1 – 6. doi:10.1109/ConfTELE50222.2021.9435579.
Chang C.Y., Chou H.T. FPGA Implementation of 5G NR PDSCH Transceiver for FR2 Millimeter-wave Frequency Bands. Proceeding of the IEEE 4th Eurasia Conference on IOT, Communication and Engineering (ECICE), 2022, pp. 60 – 63. doi:10.1109/ECICE55674.2022.10042864.
Coutinho F.D.L., Domingues J.D., Marques P.M.C., Pereira S.S., Silva H.S., Oliveira A.S.R. Towards the flexible and efficient implementation of the 5G-NR RAN physical layer. IEEE, Radio and wireless symposium (RWS), 2021, pp. 130 – 132. doi:10.1109/RWS50353.2021.9360353.
Domingues J.D., Silva H.S., Oliveira A.S.R. FPGA Implementation of a 4G/5G Multimode DU Downlink Transmission Chain. IEEE, Telecoms Conf., 2021, pp. 1 – 5. doi:10.1109/conftele50222.2021.9435553.
Chamola V., Patra S., Kumar N., Guizani M. FPGA for 5G: Re-configurable hardware for next generation communication. IEEE, Wireless Communications, 2020, Vol. 27, Part 3, pp. 140 – 147. doi:10.1109/MWC.001.1900359.
Nadal J., Baghdadi A. Parallel and flexible 5G LDPC decoder architecture targeting FPGA. IEEE, Transactions on Very Large Scale Integration (VLSI) Systems, 2021, Vol. 29, Part 6, pp. 1141 – 1151. doi:10.1109/TVLSI.2021.3072866.
Shah N. A., Lazarescu M. T., Quasso R., Scarpina S., Lavagno L. FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio. IEEE, Access, 2022, Vol. 10, pp. 119386 – 119401. doi:10.1109/ACCESS.2022.3221124.
Papatheofanous E.A., Reisis D., Nikitopoulos K. LDPC hardware acceleration in 5G open radio access network platforms. IEEE, Access, 2021, Vol. 9, pp. 152960 – 152971. doi:10.1109/ACCESS.2021.3127039.
Kim J., Kim D., Choi S. 3GPP SA2 architecture and functions for 5G mobile communication system. ICT express, 2017, Vol. 3, Part 1, pp. 1 – 8. doi:10.1016/j.icte.2017.03.007.
Wypiór D., Klinkowski M., Michalski I. Open ran-radio access network evolution, benefits and market trends. Applied Sciences, 2022, Vol. 12, Part 1, pp. 408. doi:10.3390/app12010408.
Holma H., Toskala A., Nakamura T. 5G technology: 3GPP new radio. John Wiley & Sons, 2020.
